1. Field of the Invention
The present invention relates to a phase shift circuit, and may be suitably applied to an automatic phase control circuit, which is used in a television receiver, video tape recorder, and camera, for example.
2. Description of the Prior Art
FIG. 1 illustrates a conventional automatic phase control circuit 1 which automatically phase controls chrominance signals of video signals transmitted according to NTSC (National Television System Committee) or
(Phase Alternation by Line). In the automatic phase control circuit 1, a phase shift circuit 2 outputs continuous wave signals (hereinafter referred to as CW signals), which are inputted to a multiplier circuit 3, where CW signals and burst signals S1 are multiplied and then outputted to a voltage controlled oscillator 5 through a lag-lead filter circuit 4.
In the voltage controlled oscillator 5, a quartz oscillator output S2 is shifted in phase by an output voltage .DELTA.V which has been inputted from the lag-lead filter circuit 4, so that the oscillation frequency of the quartz oscillator may be modified.
In the automatic phase control circuit 1, the output CW signals S3 having the modified oscillation frequency are fed back from the voltage controlled oscillator 5 to the phase shift circuit 2 through a low pass filter 6, so that the oscillation frequency of the quartz oscillator is made equal to the frequency of the burst signals.
In the automatic phase control circuit 1, output signals S3 are shifted 90.degree. in phase through a 90.degree. shift circuit 7, and CW signals which are 180 degrees out of phase with burst signals S1 are outputted as carrier signals of the B-Y axis through a buffer 8. Furthermore, output CW signals S3 which are in phase with the output of the low pass filter 6 are outputted as carrier signals of R-Y axis through a buffer 9.
The phase shift circuit 2 and an equivalent circuit thereof are shown in FIGS. 2 and 3, respectively. As shown in FIG. 2, a bias voltage .DELTA.V of one of the transistor pair which constitutes a differential amplification circuit is variable, and therefore the ratio between currents I1 and I2 which flow through transistors Q1 and Q2, respectively, are controlled (0&lt;k&lt;1) so that the phase of the CW signals outputted from the output terminal P0 may be shifted within a range of .+-.45.degree. with the input signals.
The collectors of the transistors Q1 and Q2 are supplied with source voltage Vcc through load resistances R1 and R2, respectively. A buffer transistor Q3 is connected to a connection node P1 between the transistor Q1 and the load resistance R1. The buffer transistor Q3 is connected at the emitter to a current source 10, and a capacitor C1 is connected between the output terminal P0 and a connection node P2 of the emitter and the current source 10.
As the phase is shifted in such a fashion, the output gain of CW signals outputted from the output terminal P0 linearly varies (FIG. 4).
When the output gain is to be 0 [dB] at a current ratio k of 1/2 as shown by broken line in FIG. 4, the output gain becomes larger as current ratio k reaches to 0 or 1, and the maximum 3 [dB] gain largely varies. When the output gain largely changes, the multiplication output from the multiplier circuit 3 however increases in distortion factor, with the result that the demodulation axis is deviated from the ideal demodulation axis.
More specifically, as illustrated in FIG. 5 the multiplier circuit 3 includes differential amplification circuits 10 and 11, which are constituted by a pair of transistors Q5 and Q6, and Q7 and Q8, respectively. Transistors Q9 and Q10 are connected to and input burst signals S1 to common emitters of transistors Q5 and Q6, and Q7 and Q8, respectively. The common emitters of the transistors Q9 and Q10 are connected to a current source 13 through a switching circuit 12 which makes switching operation by a burst gate pulse BG. To cause the differential amplification circuits 10 and 11 of the multiplier circuit 3 to perform switching operation, a voltage of 5 V.sub.T (=130 [mV]) is necessary as the input amplitude of the transistors Q5 to Q8. In the case where CW signals outputted from the phase shift circuit 2 are rather small in amplitude, the differential amplification circuits 10 and 11 are, therefore, not correctly operated, and there is thus a problem such that it is not possible to produce CW signals having .+-.90.degree. shift with burst signals at a good accuracy.
Also when CW signals are excessively large in amplitude, the distortion factor of the output gain increases in phase shifting. Furthermore, in this case the influences of base-collector capacitance C.sub.BC of the transistors Q5 to Q8 becomes excessively large, and this generates distortion in the waveform of the multiplication output, so that demodulation axes are deviated .theta. from ideal B-Y and R-Y axes (FIG. 6). When in FIG. 6 the deviation angle .theta. of the B-Y axis is corrected, the variable range of the hue by the phase shift circuit 2 becomes 45.degree.-.theta., and is therefore narrowed by the deviation .theta..
To avoid this disadvantage, a phase shift circuit 14 as shown in FIG. 7 has been proposed. In this phase shift circuit 14, a differential amplification circuit 15 which is constituted by a pair of pnp transistors is respectively connected to a connection node between load resistance R11 and the transistor Q11, and another connection node between resistance R12 and the transistor Q12 to produce negative signal voltage, and thereby the variable range of the phase to input signals is enlarged outside .+-.45.degree.. In this case, there is however a disadvantage in that the output gain due to the phase shifting becomes larger by 10 [dB] at maximum than the gain at k=1/2 as shown in FIG. 8.